About VLSI

VLSI based projects fall into two broad categories, namely VLSI based system design and VLSI design itself. Though both these terms might look similar there is a very significant difference between the two. VLSI based system design involves using already existing FPGA / CPLDs and their respective development tools to create new systems. VLSI design itself involves design of new ICs for increase in power efficiency or increase in computational capacities etc.
We at LOGSIG offer VLSI projects in the system design category, because it has wider scope for innovation and creating new applications. VLSI projects are technically rewarding because they involve the design of a system from the scratch. Also unlike a few years ago when hardware implementations in VLSI projects was prohibitively complicated and expensive, these days that is not much of a challenge.

VLSI PROJECT LIST

  • 1
  • Speculative Lookahead for Energy-Efficient Microprocessors

  • 2
  • A High-Speed FPGA Implementation of an RSD-Based ECC Processor
  • 3
  • Code Compression for Embedded Systems Using Separated Dictionaries
  • 4
  • Flexible DSP Accelerator Architecture Exploiting Carry-Save Arithmetic
  • 5
  • Computing Seeds for LFSR-Based Test Generation From Nontest Cubes
  • 6
  • A Normal I/O Order Radix-2 FFT Architecture to Process Twin Data Streams for MIMO
  • 7
  • A Systematic Design Methodology of Asynchronous SAR ADCs
  • 8
  • Fixed-Point Computing Element Design for Transcendental Functions and Primary Operations in Speech Processing
  • 9
  • Design and Implementation of High-Speed All-Pass Transformation-Based Variable Digital Filters by Breaking the                  Dependence of Operating Frequency on Filter Order
  • 10
  • A New Binary-Halved Clustering Method and ERT Processor for ASSR System
  • 11
  • LUT Optimization for Distributed Arithmetic-Based Block Least Mean Square Adaptive Filter
  • 12
  • High-Performance NB-LDPC Decoder With Reduction of Message Exchange
  • 13
  • Low-Power ECG-Based Processor for Predicting Ventricular Arrhythmia
  • 14
  • On Efficient Retiming of Fixed-Point Circuits

  • 15
  • Hybrid LUT/Multiplexer FPGA Logic Architectures

  • 16
  • Efficient Integer Frequency Offset Estimation Architecture for Enhanced OFDM Synchronization

  • 17
  • Concept, Design, and Implementation of Reconfigurable CORDIC
  • 18
  • A New CDMA Encoding/Decoding Method for on-Chip Communication Network
  • 19
  • Error Resilient and Energy Efficient MRF Message-Passing-Based Stereo Matching
  • 20
  • Genetic Algorithm-Based Multiobjective Statistical Logic Circuit Optimization Using Incremental Statistical Analysis
  • 21
  • Algebraic Methods for Optimizing Constant Multiplications in Linear Systems
  • 22
  • Analysis and Design of Low-Cost Bit-Serial Architectures for Motion Estimation in H.264/AVC
  • 23
  • Hardware Implementation of Successive-Cancellation Decoders for Polar Codes
  • 24
  • High Performance FPGA-oriented Mersenne Twister Uniform Random Number Generator
  • 25
  • Real-Time Speaker Verification System Implemented on Reconfigurable Hardware
  • 26
  • A Reconfigurable TDMP Decoder for Raptor Codes

  • 27
  • 3D Video Based Segmentation and Motion Estimation with Active Surface Evolution

  • 28
  • MIRF: A Multimodal Image Registration and Fusion Module Based on DT-CWT
  • 29
  • Parallel Computation of Adaptive Filtering Algorithms on Multi-Core Systems
  • 30
  • POWER-Area-Performance Characteristics of FPGA-based Sigma-Delta FIR Filters
  • 31
  • Design and Optimization of Multiplierless FIR Filters Using Sub-Threshold Circuits
  • 32
  • Pipelined VLSI Architecture using CORDIC for Transform Domain Equalizer
  • 33
  • A High Throughput Processor Chip for Transform and Quantization Coding in H.264/AVC
  • 34
  • On the Performance Analysis of a Class of Transform-domain NLMS Algorithms with Gaussian Inputs and Mixture Gaussian Additive Noise                  Environment
  • 35
  • Optimal Smoothing of Kernel-Based Topographic Maps with application to Density-Based Clustering of Shapes
  • 36
  • Interleaving on Parallel DSP Architectures

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